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| 6,(0(16 ,&V IRU &RPPXQLFDWLRQV 30% 9 *607UDQVPLWWHU 3UHOLPLQDU\ 'DWD 6KHHW *607UDQVPLWWHU &RQWHQWV 0 1 1.1 1.2 1.3 2 2.1 2.2 2.3 3 4 4.1 4.2 4.3 4.4 5 6 6.1 6.2 6.3 6.4 7 7.1 7.2 7.3 7.4 7.5 8 8.1 8.2 9 9.1 9.2 9.3 9.4 9.5 9.6 Revision History General Overview Features Applications Functional Description Pinning Pin Description Pin Configuration Package Outline Functional Block Diagram Circuit Description Block Level Description Supply Concept Power Down Conditions Matching with Timing Signals of GOLD-uC Internal Input/Output Circuits Electrical Characteristics Absolute Maximum Ratings Operational Range AC/DC Characteristics Typical modulator measurement results Test Circuits Test Circuit 1 Test board Layout top Test board Top place Test board Layout bottom Test board Bottom place Application Frequency plan for GSM application Application hint for phase adjust S-Parameters and Input/Output impedances S-Parameters: Transmit Mixer Output MO/MOX S-Parameters: IF Input IF/IFX S-Parameters: RF Input RFB1/RFB2 S-Parameters: Output to Receiver RF/RFX S-Parameters: Modulator Output E/EX S-Parameters: Modulator Input LO/LOX 30% 9 page 3 4 4 4 4 5 5 6 6 7 8 8 9 10 10 11 12 12 13 14 18 20 20 21 22 23 24 25 25 26 27 28 28 29 30 31 31 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 2 05.97 *607UDQVPLWWHU 5HYLVLRQ +LVWRU\ 30% 9 Changes from Data sheet PMB2240 V1.5 ( 08.96 ) to Data sheet PMB2240 V1.6 ( 5.97 ) 'DWD VKHHW 9 3DJH ,WHP 4 1 5 2.1 'DWD VKHHW 9 3DJH ,WHP 4 1 5 2.1 1 2 6XEMHFW General Overview Pinning &KDQJH Revised Pin 9 changed to VCCPR; Pin 13 changed to SLEEP; Pins 17,18,20,21 changed to GND pins Prescaler with separate VCCPR-pin; Former SLEEP/PR and SLEEP/RF are merged to SLEEP; Oscillator/Buffer for RFIN removed; Revised Revised ESD integrity revised; Item symbols revised Temperature range 30C - 85C minimum H-voltage increased to 2.3V Spec item symbols revised Now referred to Test circuit 1 Smith diagrams of simulated S-Params replaced by measured S-Param-table and I/O impedances 3 Functional block diagram 7 3 7 3 4 5 6 7 8 9 Circuit description Internal I/O Circuits Asolute Maximum ratings Operational range Prescaler 8,9,10 11 12 13 15 12-18 14 27-30 4 5 6.1 6.2 23 6 6.3 #4 9 8,9,10 11 12 13 15 12-17 14 27-31 4 5 6.1 6.2 23 6 6.3 #4 9 Electrical Characteristics 10 AC/DC characteristics 11 S-Parameters The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 3 05.97 *607UDQVPLWWHU *HQHUDO 2YHUYLHZ )HDWXUHV 30% 9 Transmitter with I/Q modulator Direct I/Q modulation Generation of orthogonal carriers with possibility of phase adjust with external resistors at OFF1/OFF2 32dB minimum carrier rejection, 35dB minimum SSB rejection with 1 Vpp I/Q drive level 50dB rejection of third order products with 1 Vpp I/Q drive level -3dBm output power at 1 Vpp I/Q drive level with 200 Ohms load according testcircuit 1 RF oscillator signal is AC-coupled to internal buffer stage (symmetrical or unsymmetrical) The RF oscillator-signal is buffered for off-chip use, especially for receiver chip PMB2405. Prescaler for the RF oscillator signal Possibility to build RF-PLL with integrated prescaler + PMB2306 Possibility to use the IF oscillator signal from the IF-VCO on PMB2405 Possibility to use external source for IF oscillator-signal Digital parts of fixed IF frequency PLL (fixed-PLL) for IF-VCO on PMB2405 Supply voltage range from 2.7 V to 4.5 V P-TQFP-48 package Temperature range -30 to 85C $SSOLFDWLRQV Vector modulated digital mobile cellular systems as GSM, DAMPS, PDC,WLAN etc. Various modulation schemes, such as PM, PSK, FSK, QAM, QPSK, GMSK etc. Analog systems with FM and AM modulation Space and power saving optimizations of existing discrete transmitter circuits )XQFWLRQDO 'HVFULSWLRQ The PMB2240 is a single-chip transmitter which includes a prescaler for the main oscillator signal and a fixed frequency PLL for the IF oscillator. The transmitter is designed for use in conjunction with the single-chip receiver PMB2405 and the CMOS PLL PMB2306. The RF oscillator signal can be supplied from an external source symmetrically as well as unsymmetrically. The oscillator signal can be buffered for off-chip use, depending on a separate power down pin. There is a prescaler by 64/65 for the RF oscillator signal on chip, which can be used to implement a PLL together with the PMB2306. The on-chip fixed-PLL consists of the system clock divider, the IF oscillator signal divider, the phase detector and the charge pump. The IF oscillator signal divider is driven by the oscillator on the PMB2405 or by an external discrete VCO. The two oscillator signals are combined in the transmit mixer, and the image sideband and other mixing products are suppressed with an external interstage filter. The filtered signal reenters the chip at the modulator inputs LO/LOX. The modulator generates two orthogonal carriers which are mixed with the modulation signals I and Q in two Gilbert multipliers. The phase between the two carriers can be fine-adjusted to 90 (orthogonality) by two external resistors at OFF1/OFF2 for best SSB suppression. The outputs of the Gilbert cells are added and amplified by a linear output stage. The PMB2240 is designed for digital mobile telephones according to the GSM-Standard. The chip can also be used for other digital systems and the dual mode system. As part of the Siemens GSM/DCS chipset the derivatives PMB2245 and PMB2247 are offered for the DCS 1800 and DCS 1900 frequency range. The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 4 05.97 *607UDQVPLWWHU QvAI 30% 9 3LQQLQJ 3LQ 'HVFULSWLRQ Tiy Apv 1, 44, 46 2 3 4 5 6 7 8 9 10 11 12 13 14,17,18,20 15 16 19 21,24 22 23 25,33 26 27 28 29 30 31 32 34 35 36 37 38 39 40 41 42 43 45 47 48 GND2 PUPLO2/FP IF IFX VCC2 PUPLO2/BU RF RFX VCCPR TOUT IREF/PLL FMOD SLEEP GND3 VCC3 RFB1 RFB2 GND4 LO LOX GND1 MO MOX GND5 QX Q I IX E EX VCC1 TREF TXON1 OFF1 OFF2 T3 PDBUFRX n.c. CHP RREF/PLL FREF Ground for the PLL-parts and their bias Power down for fixed-PLL-dividers and phase detector Input for external IF oscillator signal Input for inverted external IF oscillator signal Supply voltage for PLL parts (IF and RF) and their biasing Power down for IF/IFX input buffer RF oscillator signal to receiver Inverted RF oscillator signal to receiver Separate supply voltage for RF-PLL prescaler Output of RF-PLL prescaler Output for reference current for external RF-PLL-chip Modulus control for prescaler Power down of RF oscillator input- and output buffer and the prescaler Ground for RF oscillator + BufRX Supply voltage for BufRX and BufRF RF oscillator input buffer (inverting input) RF oscillator input buffer (non-inverting input) Ground for internal shielding Modulator LO frequency input Inverted Modulator LO frequency input Ground for modulator and mixer parts + Bias1 Mixer output, open collector Inverted mixer output, open collector Ground for substrate contacts in the modulator Quadratur modulating inverting input, open base Quadratur modulating input, open base In phase modulating input, open base In phase inverted modulating input, open base Non-inverting output of modulator, open collector; ESD disconnected Inverting output of modulator, open collector; ESD disconnected Supply voltage for modulator and mixer parts + Bias1 Temperature compensated DC reference voltage output for modulator I/Q -inputs via GMSK baseband circuit Power down for modulator and mixer parts + Bias1 Phase error adjustment of orthogonal carriers with constant R Phase error adjustment of orthogonal carriers with constant R Test pin 3 Power down for "BufRX" not bonded Phase-detector output for external loop filter (charge pump) To be connected to GND via resistor to determine IREF for RF-PLL Input of system reference clock The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 5 05.97 *607UDQVPLWWHU 3LQ &RQILJXUDWLRQ (top view) 48 1 30% 9 3DFNDJH 2XWOLQH 4XDG )ODW SDFNDJH 374)3 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 6 05.97 *607UDQVPLWWHU )XQFWLRQDO %ORFN 'LDJUDP 30% 9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 7 05.97 *607UDQVPLWWHU &LUFXLW 'HVFULSWLRQ %ORFN /HYHO GHVFULSWLRQ 30% 9 The GSM transmitter PMB2240 contains a number of functions that have been realised with multiple chips earlier: - Oscillator signal input balanced or unbalanced - RF-PLL prescaler - IF-PLL dividers and phase detection - TX - mixer - I/Q modulator The PMB2240 V1.6 is designed to be used with an external RF oscillator module. On chip this signal is AC-coupled to an internal buffer stage. Therefore the RF input is suitable for symmetrical or single ended use. There is no need for an external DC-bias of the RF input. The active parts of the IF oscillator are located on the receive chip PMB2405. A buffer BufRX, which can be powered down by pin PDBUFRX, is used to transmit the RF oscillator signal to the receiver chip to drive the RF receive mixer. A special input buffer BufTX receives the IF oscillator signal from the receive chip or an external source. The RF oscillator signal is divided by the integrated 64/65 prescaler which can be connected to the CMOS PLL circuit PMB2306 for the RF oscillator PLL. The supply pin VCCPR is a separate prescaler supply, which openes the possilility to run the prescaler and the rest of the RF synthesizer on a supply voltage that is different from the supplies of the rest of the chip. For the IF-PLL the active oscillator structures on the PMB2405 or an external VCO module can be used. The PMB2240 V1.6 contains the digital parts tor the IF oscillator PLL (fixed-PLL): the IFfrequency and system clock dividers and a phase detector plus charge pump are integrated to lock the IF oscillator to the external system clock. The oscillator signal drives the divider by 2 in front of the transmit mixer. The phase locked IF- and RF- signals are converted into the transmit band (e.g. 880 915 MHz for GSM) by the TX- mixer. The mixer output signal leaves the chip at MO/MOX and passes an external interstage filter to provide suppression of unwanted products. This signal reenters the chip at the modulator input LO/LOX. The LO signal is divided into two orthogonal carriers at the transmit frequency. The phase between the two carriers can be fine-adjusted to 90 (orthogonality) by two external resistors at OFF1/OFF2 for maximum SSB suppression. The modulator consists of two Gilbert multipliers, where the modulating signals I(t) and Q(t) are multiplied with the RF-carriers. The outputs of both Gilbert cells are added and amplified by a linear output stage. The modulated transmit signal is available at E/EX and is fed into a transmitter power amplifier. The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 8 05.97 *607UDQVPLWWHU 6XSSO\ FRQFHSW 30% 9 There are four independent supply voltages ( VCC1-3,VCCPR ) and ground rails ( GND1-4 ) to decouple the modulator/mixer parts, the synthesizer parts, and the RFVCO parts. The supply pin VCCPR is a separate prescaler supply, which openes the possilility to run the prescaler together with the rest of the RF synthesizer on a supply voltage that is different from the supplies of the rest of the chip GND4 is a special shielding ground to decrease crosstalk between the separately supplied blocks. GND5 collects the substrate contacts in the modulator and mixer. It is recommended to connect all GND pins to a common GND on the board. In the following figure the chip schematic is partitioned according to its supply rails. The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 9 05.97 *607UDQVPLWWHU 3RZHU GRZQ FRQGLWLRQV 30% 9 The PMB 2240 has five Power down inputs. PD = Low means that the respective part of the chip is in power down mode. TXON1: TXON1 /\ PUPLO2/FP SLEEP: PUPLO2/BU: PUPLO2/FP: PDBUFRX /\ SLEEP Modulator, mixer, Bufmi1, Bufmi2 %2 divider BufRF, prescaler with its input buffer BufPLL Input buffer BufTX for external IF oscillator-signal fixed-PLL, (%492; %13; phase detector, charge pump) BufRX For normal operation only three modes are used: sleep mode, TX-mode, RX-mode. Depending on the application some power down-pins can be combined, and others can be fixed to supply rails. 0DWFKLQJ ZLWK 7LPLQJ 6LJQDOV RI *2/'X& In application with PMB2405 and GOLD-uC the power down pins of PMB2240 must be connected to the timing signals of GOLD-uC as follows: PMB 2240 TXON1 PUPLO2/BU, PUPLO2/FP SLEEP, PDBUFRX GOLD-uC TXON1 PUPLO2 general purpose port pin connected to connected to connected to The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 10 05.97 *607UDQVPLWWHU ,QWHUQDO ,QSXW2XWSXW &LUFXLWV 30% 9 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 11 05.97 *607UDQVPLWWHU (OHFWULFDO &KDUDFWHULVWLFV $EVROXWH 0D[LPXP 5DWLQJV 30% 9 The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. 3DUDPHWHU 1 2 3 4 5 Supply Voltage Input/Output Voltage Open Collector Output Voltage at E/EX Open Collector Output Voltage at MO/MOX Differential Input Voltage (any differential Input) Junction Temperature Storage Temperature Thermal Resistance (junction to ambient) ESD integrity * 6\PERO VCC VIO VOCE VOCM VID /LPLW 9DOXHV PLQ -0.3 -0.3 VCC - 1.5 -0.3 PD[ 5.0 5.0 VCC + 1.0 5.0 2 V V V V V 8QLW 5HPDUNV 6 7 8 9 TJ TS RthJA VESD -40 -55 125 125 165 C C K/W V according MIL-Std. 883D, method 3015.7 -1000 +1000 * exception: Pin 47 to GND and a negative Pulse to pin 11 => 800V ESD-integrity The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 12 05.97 *607UDQVPLWWHU 2SHUDWLRQDO 5DQJH 30% 9 Within the operational range the IC operates as described in the circuit description. The AC/DC characteristics limits are not guaranteed. VCC = 2.7V to 4.5V; TA = -30 to 85C; 3DUDPHWHU 1 2 3 4 5 6 7 8 9 RFB1/RFB2 Input Level RFB1/RFB2 Input Frequency IF/IFX Input Level IF/IFX Input Frequency LO/LOX Input Level LO/LOX Input Frequency Mixer output Frequency Range PD-Signals Voltage-L PD-Signals Voltage-H 6\PERO PRFIN fRFIN PIFIN fIFIN PLO fLO fMO VPDL VPDH /LPLW 9DOXHV PLQ -10 900 -15 400 -15 800 800 0 2.0 PD[ 0 1300 0 600 0 1000 1000 0.8 VCC dBm MHz dBm MHz dBm MHz MHz V V wanted sideband 8QLW 5HPDUNV Note: Power levels are referred to impedance of 50 Ohms The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 13 05.97 *607UDQVPLWWHU $&'& &KDUDFWHULVWLFV 30% 9 AC/DC characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production. VCC = 2.7V/4.5V; TA = 25C; 3DUDPHWHU 6\P ERO PLQ 1 Supply Current all powered up Ivcc1 Ie+Iex Imo+ Imox Ivcc2 Ivcc3 Ivccpr Ivcc1 Ie,Iex Imo, Imox Ivcc2 Ivcc3 Ivccpr 16 9 7 5 9.3 2.5 /LPLW 9DOXHV W\S 22 13 10 6.3 11 3.3 PD[ 29 18 13 7.5 13.2 4 2 2 2 2 2 2 mA mA mA mA mA mA uA uA uA uA uA uA TXON1 & PUPLO2/FP & PUPLO2/BU & SLEEP & PDBUFRX = HIGH TXON1 & PUPLO2/FP & PUPLO2/BU & SLEEP & PDBUFRX = LOW 1 8QLW 7HVW &RQGLWLRQ 7HVW FLUFXLW 2 Supply Current all powered down 1 7UDQVPLW 0L[HU 2XWSXW 0202; 3 Output impedance (open collector diff. output) Output level Carrier suppression Output Frequency Input Level PMO aCmix fMO PIFIN -18 25 800 -15 110 400 see S-parameter 9.1 4 5 6 7 -15 30 -12 dBm dB 900 MHz 1 1 1000 0 600 600 MHz dBm mVpp * MHz wanted sideband 1 1 ,) LQSXW DW ,),); 8 Input Frequency fIFIN 1 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 14 05.97 *607UDQVPLWWHU 3DUDPHWHU 6\PEO PLQ )L[HG 3// 9 10 11 lock in time Power on delay Input level at FREF Output current at CHP tI tpo VFREFI 0.4 250 0.3 1 2 usec usec Vpp /LPLW 9DOXHV W\S PD[ 8QLW 30% 9 7HVW &RQGLWLRQ 7HVW &LUFXLW Application hint Application hint high input levels may cause spurious problems 1 12 ICHP +-450 +-600 +-750 uA 1 2XWSXW WR UHFHLYHU 5)5); 13 14 15 Internal DC bias Output impedance Output level PRFOUT -11 VRFDC VCC 0.6 V 1 see S-parameter 9.4 -8 -5 dBm f = 1200 MHz 1 5) LQSXW DW 5)%5)% 16 17 Input Level Input Frequency PRFIN fRFIN -10 900 0 1300 dBm MHz 1 1 /2 LQSXW DW /2/2; 18 19 20 21 Input impedance Input Level Input Frequency suppression of image in mixer output signal PLO fLO aIM -15 800 14 see S-parameter 9.6 0 1000 dBm MHz dB Application hint into 50 Ohm 1 1 3UHVFDOHU 22 23 24 25 Input at FMOD voltage-L Input at FMOD voltage-H Output DC level at TOUT Output AC amplitude at TOUT VFMOD VFMOD VTOUTDC VTOUTAC 0 2.3 VCC-1 160 0.8 VCC VCC0.7 300 V V V mVpp f = 13.5MHz to 20.5MHz 1 1 1 1 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 15 05.97 *607UDQVPLWWHU 3DUDPHWHU 6\PEO PLQ 5HIHUHQFH FXUUHQW IRU H[WHUQDO 3// 26 External voltage of current sink fed to IREF/PLL Current sourced at IREF/PLL Temperature dependency of current sourced at IREF/PLL * VIREF/PLL 30% 9 /LPLW 9DOXHV W\S PD[ 8QLW 7HVW &RQGLWLRQ 7HVW &LUFXLW 1.2 V 1 27 IIREF/PLL 100** 360 uA dependent of resistor value at RREF/PLL *** temperature range: -30 to 85 C nominal current: 300uA 1 28 IIREF/PLL +-2 % 0RGXODWRU LQSXWV ,,; DQG 44; 29 I-IX and Q-QX VI-IX, differential input level V Q-QX 30 Recommended VDCext range for ext DC voltage to compensate internal offset at I-IX and Q/QX * 31 Reference voltage for I,Q modulating inputs VTREF 1.25 1.35 500 1000 15 mVpp mV 1.45 V Reference to external GMSK basebandcircuit to bias I and Q of PMB2240 (temperature compensated) 1 32 Resistive load at TREF * 33 Input base current 34 Differential input resistance * 35 Differential input capacitance * 36 Input frequency * RTREF II/Q_DC RI-IX CI-IX fI-IX fQ-QX 3 1 50 1 10 6 12 kOhm uA kOhm pF MHz at 200 kHz * Design hint ** required by PMB2306 R19 = 6.8k *** R19 at pin RREF/PLL gives constant PLL reference current at pin IREF/PLL: ( R19max = open -> IIREF/PLLmin = 0, R19min = 2 KOhm -> IIREF/PLLmax =360uA) The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 16 05.97 *607UDQVPLWWHU 3DUDPHWHU 6\PEO PLQ 0RGXODWRU RXWSXW ((; 37 Output impedance (open collector diff. output) 38 Output power ' 39 Carrier suppression 40 Single sideband suppression aCmod aSSB /LPLW 9DOXHV W\S PD[ 8QLW 30% 9 7HVW &RQGLWLRQ 7HVW &LUFXLW fLO = 900 MHz; fI-IX = fQ-QX =10MHz; see S-parameter 9.5 PE_b -12 -6 26 32 35 -9 -3 32 38 -6 0 dBm dBm dB dB dB cond1 ** cond2 *** cond1 ** cond2 *** with 90 phase shift between I and Q; ROFF1,ROFF2 tuned to maximum SSB suppression ( appl. hint: fig.1,sec. 8.3) cond1 ** 1 1 1 1 1 41 Suppression of third order distortion products 42 Signal to noise ratio * aIM3 62 dB 1 50 S/N -139 dB dBc/Hz cond2 *** cond1 ** PLO = -8 dBm foffset = 20MHz cond2 *** PLO = -8 dBm foffset = 20MHz 1 1 -142 dBc/Hz 1 * Design hint ** cond1 means VI-IX = VQ-QX = 500 mVpp *** cond2 means VI-IX = VQ-QX = 1 Vpp The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 17 05.97 *607UDQVPLWWHU 7\SLFDO PRGXODWRU PHDVXUHPHQW UHVXOWV The following measurements refer to Testcircuit 1 ( item , page 21) 30% 9 HqyhAvthyAAvrAhvATIArADRAvAyrry QyA)AGPAqvrAyrry ## #! # "' C p "% 7 q A A "# I Qy Aq7A 'Aq7A T "! " !' !% ! " # $ % & ' ( qvssrrvhyAvAyhtrAhADDYAhqARRYAAW HqyhAphvrArvAhpArADRAvAyrry QyA)AGPAqvrAyrry $ #$ # 7 q A "$ A p h Qy " Aq7A 'Aq7A !$ ! ! " # $ % & ' ( qvssrrvhyAvAyhtrAhADDYAhqARRYAAW The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 18 05.97 *607UDQVPLWWHU 30% 9 HqyhAuvqAqrAvrqyhvAqpADH"ArADRAvAyrry GPAqvrAyrryA)AQyA2A'Aq7 ' &$ & GPAsrrp (AHCA 7 %$ q A A " H D % $$ $ #$ ! " # $ % & ' ( qvssrrvhyAvAyhtrAhADDYAhqARRYAAW HqyhAArAQArADRAvAyrry GPAqvrAyrry)AQyA2A'Aq7 $ $ 7 q A A Q GPAsrrp (AHCA $ ! !$ $ $ ! !$ AqvssrrvhyAvAyhtrAhADDYAhqARRYAAW The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 19 05.97 *607UDQVPLWWHU 7HVW &LUFXLWV 7HVW &LUFXLW 30% 9 V A ROFF1/ROFF2 = 0 ... 600 Ohm; see application hint on page 26 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 20 05.97 GSM-Transmitter 7.2 Test board Layout top, (M 2:1) PMB 2240 V 1.6 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens Aktiengesellschaft 21 05.97 GSM-Transmitter 7.3 Test board Top place PMB 2240 V 1.6 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens Aktiengesellschaft 22 05.97 GSM-Transmitter PMB 2240 V 1.6 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens Aktiengesellschaft 23 25.02.98 GSM-Transmitter PMB 2240 V 1.6 The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens Aktiengesellschaft 24 25.02.98 *607UDQVPLWWHU $SSOLFDWLRQ )UHTXHQF\ SODQ IRU *60 DSSOLFDWLRQ 30% 9 In the application the IF oscillator on the receive chip is locked at a frequency of 492 MHz by the fixed-PLL circuit. The RF oscillator module is tuned from 1126 MHz to 1206 MHz. The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 25 05.97 *607UDQVPLWWHU $SSOLFDWLRQ KLQW IRU SKDVH DGMXVW 30% 9 The LO level for maximum SSB suppression can be tuned to every value within its operational range ( -15 dBm to 0 dBm ) by appropriate choice of ROFF1/ROFF2. At pins OFF1 and OFF2 always a resistor or a short cicuit to ground is required. The recommended range of values is: 0 > ROFF1,ROFF2 < 600 Ohm. In fig. 1 the maximum single sideband suppression (assb) is tuned to -7dBm LO input power accordinng test circuit 1. ROFF1=0 and ROFF2=200 Ohms. The LO level can vary +/- 4dB around its optimum value with assb < -35dB. 6LQJOH 6LGHEDQG VXSSUHVVLRQ DVVE YHUVXV OR LQSXW SRZHU 3OR DVVE G% 3OR G%P ILJ Phase adjust with ROFF1=short, ROFF2=200 Ohms The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 26 05.97 *607UDQVPLWWHU 63DUDPHWHUV DQG ,QSXW2XWSXW ,PSHGDQFHV 30% 9 The S-parameters provided in this section are based on measurements. Measurement setup for differential in-/outputs: In/Out Port1 DUT Inx/Outx Port2 The input/output impedances are calculated from these parameters. The impedances are given as equivalent circuit with lumped elements for differential and single ended in-/outputs. The high frequency in-/outputs in this section are base inputs or collector outputs. As equivalent circuit for these in-/outputs a resistor Rp in parallel to a capacitance Cp is derived: differential Rpd Cpd single ended Rps Cps The S-parameters are available on disk. The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 27 05.97 *607UDQVPLWWHU 7UDQVPLW 0L[HU 2XWSXW 0202; 30% 9 S-parameters: f S11 GHz MAG 0.80 0.957 0.85 0.951 0.90 0.946 0.95 0.940 1.00 0.935 S21 ANG -23.7 -25.5 -27.1 -28.9 -30.7 MAG 0.093 0.098 0.103 0.107 0.111 ANG 70.4 69.3 68.2 67.2 66.8 MAG 0.092 0.097 0.102 0.106 0.109 S12 ANG 71.7 70.7 69.4 68.4 68.0 MAG 0.952 0.944 0.932 0.913 0.892 S22 ANG -22.4 -24.3 -26.2 -28.0 -28.5 Output impedance at MO/MOX: u P x A v A S 5SG 5SV A A sAvAHC v A 8 &SG &SV sAvAHC ,) ,QSXW ,),); S-parameters: f S11 GHZ MAG 0.40 0.978 0.45 0.974 0.50 0.970 0.55 0.967 0.60 0.963 S21 ANG -15.0 -16.8 -18.8 -20.9 -23.0 MAG 0.057 0.063 0.070 0.076 0.082 ANG 74.0 72.5 70.8 69.2 67.5 MAG 0.057 0.064 0.070 0.076 0.082 S12 ANG 73.7 72.0 70.2 68.4 66.7 MAG 0.977 0.972 0.968 0.963 0.957 S22 ANG -14.7 -16.6 -18.5 -20.5 -22.5 Input impedance at IF/IFX: u P x A v A S 5SG 5SV &SG &SV sAvAHC A A v A 8 sAvAHC The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 28 05.97 *607UDQVPLWWHU 5) ,QSXW 5)%5)% 30% 9 S-parameters: f GHZ 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.300 S11 MAG 0.850 0.840 0.832 0.823 0.815 0.807 0.799 0.792 0.785 ANG -29.7 -31.5 -33.2 -34.8 -36.5 -38.1 -39.7 -41.3 -42.8 MAG 0.020 0.020 0.021 0.022 0.022 0.022 0.023 0.023 0.023 S21 ANG 43.1 41.8 41.0 40.3 39.1 37.8 37.7 35.8 36.0 MAG 0.021 0.022 0.024 0.025 0.026 0.027 0.028 0.028 0.028 S12 ANG 47.5 46.1 45.4 43.9 41.5 38.8 36.6 33.1 31.1 MAG 0.843 0.836 0.830 0.823 0.817 0.810 0.803 0.797 0.790 S22 ANG -31.8 -33.6 -35.4 -37.2 -39.0 -40.8 -42.6 -44.3 -46.0 Input impedance: u P x A v A S sAvAHC SG SV A A v A 8 sAvAHC &SG &SV The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 29 05.97 *607UDQVPLWWHU 2XWSXW WR 5HFHLYHU 5)5); 30% 9 S-parameters: f GHZ 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 S11 MAG 0.556 0.543 0.532 0.524 0.520 0.524 0.534 0.551 0.572 S21 MAG 0.164 0.165 0.164 0.161 0.155 0.144 0.132 0.116 0.101 S12 MAG 0.149 0.168 0.187 0.207 0.228 0.248 0.267 0.283 0.297 S22 MAG 0.789 0.795 0.800 0.805 0.806 0.803 0.796 0.783 0.765 ANG -19.6 -19.5 -19.2 -18.3 -17.2 -16.0 -14.8 -14.2 -14.1 ANG 21.2 14.7 7.5 -0.6 -9.8 -19.6 -31.1 -43.9 -59.6 ANG 122.2 117.8 113.2 108.3 103.1 97.3 91.5 85.2 78.7 ANG -20.8 -23.4 -26.3 -29.4 -32.8 -36.3 -40.0 -43.6 -47.2 Output impedance at RF/RFX: u P x A v A S A A v A 8 sAvAHC SG SV sAvAHC &SG &SV The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 30 05.97 *607UDQVPLWWHU 0RGXODWRU 2XWSXW ((; 30% 9 S-parameters: f S11 GHz MAG 0.80 0.972 0.85 0.960 0.90 0.951 0.95 0.948 1.00 0.949 S21 ANG -26.2 -28.0 -29.4 -30.8 -32.4 MAG 0.116 0.120 0.125 0.131 0.137 ANG 65.2 64.1 63.3 62.4 60.9 MAG 0.126 0.131 0.136 0.142 0.148 S12 ANG 64.7 63.2 61.9 60.7 58.9 MAG 0.957 0.947 0.946 0.948 0.950 S22 ANG -25.2 -26.4 -27.8 -29.3 -31.2 Output impedance at E/EX: sAvAHC SG SV u P x A v A S A A v A 8 sAvAHC &SG &SV 0RGXODWRU ,QSXW /2/2; S-parameters: f S11 GHZ MAG 0.80 0.896 0.85 0.888 0.90 0.879 0.95 0.871 1.00 0.861 ANG -29.6 -31.7 -33.9 -36.1 -38.4 S21 MAG 0.125 0.130 0.136 0.140 0.145 ANG 62.4 61.2 59.9 58.7 57.1 S12 MAG 0.126 0.131 0.136 0.141 0.145 ANG 62.4 61.2 59.6 58.4 56.8 S22 MAG 0.887 0.871 0.863 0.854 0.850 ANG -32.1 -34.1 -35.9 -37.9 -40.0 Input impedance at LO/LOX: u P x A v A S A A 5SG 5SV v A 8 sAvAHC sAvAHC &SG &SV The reproduction, transmission or use of this document is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. Siemens AG 31 05.97 |
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